iucsl

New High-Frequency Ultra-Low-Noise Clock Generating CMOS IC

Activities November 6, 2017

ICSL (Prof. Jaehyouk Choi)’s paper “A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop-Filter PLL Using a Fast Phase-Error Correction Technique” has been accepted for publication in IEEE Journal of Solid-State Circuits, which is the most prestigious journal in the field of semiconductor circuits. The authors are Yongsun Lee, Taeho Seong, Seyeon Yoo, and Jaehyouk Choi*.

In this paper, a phase-locked loop (PLL) with a fast-phase error correction (FPEC) technique was proposed to overcome major drawbacks of conventional ring-oscillator-based clock generators. Using the proposed FPEC technique, this work achieved the world-best noise performance.

 

Article title: A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop-Filter PLL Using a Fast Phase-Error Correction Technique

Authors: Yongsun Lee, Taeho Seong, Seyeon Yoo, and Jaehyouk Choi*

Journal title: IEEE Journal of Solid-State Circuits (JSSC)

IF: 4.181 (JCR 2016)