홍보사진

New high-frequency clock generating circuit achieving ultra-low noise performance and high multiplication factor

Activities December 3, 2018

ICSL’s paper, “An Ultra-Low-Jitter 22.8-GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier with a Multiplication Factor of 114”, has been accepted for publication in IEEE Journal of Solid-State Circuits, which is the most prestigious journal in the field of semiconductor circuits. The authors are Seojin Choi, Seyeon Yoo, Yongsun Lee, Yongwoo Jo, Jeonghyun Lee, Younghyun Lim, and Jaehyouk Choi*

In this paper, an ultra-low-jitter ring-LC-hybrid injection-locked clock multiplier (ILCM) with a high multiplication factor of 114 is presented. The proposed ILCM had the highest output frequency with the largest multiplication factor among state-of-the-arts ILCMs. In addition, the proposed dual-purpose frequency calibrator (DPFC) that can calibrate the frequency drifts of the two VCOs, concurrently, consumes only 400μW. The prototype circuit was fabricated using a TSMC 65-nm CMOS process.

Article Title: An Ultra-Low-Jitter 22.8-GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier with a Multiplication Factor of 114

Authors: Seojin Choi, Seyeon Yoo, Yongsun Lee, Yongwoo Jo, Jeonghyun Lee, Younghyun Lim, and Jaehyouk Choi*

Journal title: IEEE Journal of Solid-State Circuits (JSSC)

IF: 4.075