Two papers are selected for presentation at ISSCC 2018
2017.11.17
Two ICSL (Prof. Jaehyouk Choi)’s papers have been accepted for presentation at IEEE ISSCC (International Solid-State Circuits Conference) in San Francisco in February 2018.
ISSCC is the single most prestigious conference in the field of semiconductor circuits and systems and also called “Semiconductor Olympic”. Since the first event in 1954, every year more than 3,000 researchers from industry and academia all over the world participate to present and exchange state-of-the-art technologies and research outcomes. The next year’s ISSCC is the 65th and has a theme “Silicon Engineering a Social World”.
In this year, UNIST made a remarkable achievement by making two papers selected, and it is ranked at the 4th place among the institutions of Korea, following Samsung Electronics, KAIST, and SK Hynix.
The first authors of the two selected papers are Heein Yoon and Taeho Seong. In her research, Heein presents transceiver-IC technologies for future 5G mobile communications, and they are expected to be the fundamental technologies for the successful launch of 5G in the global market. In the other paper, Taeho presents a new concept of an ultra-low noise clock generation technique. The circuit proposed by Taeho is expected to make the manufacturing cost of semiconductor chips greatly reduced.
Related article: http://news.naver.com/main/read.nhn?mode=LSD&mid=sec&sid1=101&oid=008&aid=0003964017
L1-level conference: 2018 IEEE International Solid-State Circuit Conference (ISSCC), February, 2018
1. Authors: Heein Yoon, Juyeop Kim, Suneui Park, Youngyhun Lim, Yongsun Lee, Jooeun Bang, Kyoohyun Lim, Jaehyouk Choi
Title: A -31dBc Integrated-Phase-Noise 29GHz Fractional-N Frequency Synthesizer Supporting Multiple Frequency Bands for Backward-Compatible 5G Using a Frequency Doubler and Injection-Locked Frequency Multipliers
2. Authors: Taeho Seong, Yongsun Lee, Seyeon Yoo, and Jaehyouk Choi
Title: A −242dB FOM and −75dBc-Reference-Spur Ring-DCO-Based All-Digital PLL Using a Fast Phase-Error Correction Technique and a Low-Power Optimal-Threshold TDC