UNIST EE graduate students’ paper accepted at VLSI Symposium 2019
ICSL’s paper, “A 0.5V-VIN, 0.29ps-Transient-FOM, and Sub-2mV-Accuracy Adaptive-Sampling Digital LDO Using Single-VCO-Based Edge-Racing Time Quantizer”, has been accepted for presentation at the forthcoming Symposium on VLSI Circuits 2019 which will be held in Kyoto, Japan.
Symposium on VLSI Circuits is recognized as the top conference on semiconductor circuits, along with ISSCC (International Solid-State Circuits Conference).
In this year’s work, a fast-transient and high-accuracy digital LDO using a single-VCO-based edge-racing time quantizer is presented. The proposed LDO achieved the best transient figure-of-merit (FOM) among state-of-the-arts digital LDOs. The prototype circuit was fabricated using a TSMC 65-nm CMOS process.
Authors: Jeonghyun Lee, Jooeun Bang, Younghyun Lim, and Jaehyouk Choi
Title: A 0.5V-VIN, 0.29ps-Transient-FOM, and Sub-2mV-Accuracy Adaptive-Sampling Digital LDO Using Single-VCO-Based Edge-Racing Time Quantizer
Conference: 2019 IEEE Symposium on VLSI Circuits
Presentation date: June, 2019