교원소개

반도체산업의 비약적인 발전으로 많은 혜택을 누리는 현재, wireless/wired 통신 기술과 접목된 반도체 산업은 새로운 서비스들을 위한 플랫폼이 되었습니다. 이러한 발전에 있어 저희는 1. 6G/위성통신 상용화하기 위한 sub-THz-range RF transceiver 개발 및 자율주행/connected car를 위한 C-V2X용 transceiver 개발, 2. Emerging application (Massive IoT, 6G, 등)을 위한 초저잡음/저전력 frequency synthesizer 및 고성능 analog-to-digital converter (ADC) 연구, 3. AI SoC의 효율을 높이기 위해 analog-mixed signal Neuromorphic computing hardware 개발/연구, 4. 반도체 디자인에 들어가는 시간과 비용을 획기적으로 줄이기 위한 Analog/RF mixed-signal IC의 automation을 연구 및 개발하고 있습니다.

[Curriculum Vitae]

● 2022-Present: Assistant Professor, Department of Electrical Engineering, UNIST
● 2019-2022: Senior Engineer at Qualcomm, San Diego, CA, USA − Working on frequency synthesizers for premier-tier 2G/3G/4G/5G cellular transceiver using 14nm/7nm CMOS
● 2017-2018: Internship at Qualcomm, San Diego, CA, USA − Advanced frequency synthesizer for emerging 5G technology

[Education]

● 2019: Ph.D., in Department of Electrical Engineering, UNIST
● 2014: B.S., Department of Electrical Engineering, UNIST

[Research  Keywords and Topics]

● Analog/RF mixed-signal integrated circuits (ICs) and systems
● RF Transceivers for 5G/6G communications
● Analog/RF IC design automation
● Circuits and systems for emerging wireless/wired applications
● High performance analog-to-digital converter (ADC)

[Publications (selected)]

● S. Yoo*, S. Park*, S. Choi*, Y. Cho, H. Yoon, C. Hwang, J. Choi, “An 82fsRMS-Jitter and 22.5mW-Power, 102GHz W-Band PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector in 65nm CMOS,” IEEE International Solid-State Circuit Conference (ISSCC), Feb. 2021. (* Equally-Credited Authors)
● Y. Lim*, J. Kim*, Y. Jo, J. Bang, S. Yoo, H. Park, H. Yoon, and J. Choi, “A 170MHz-Lock-In-Range and -253dB-FOMJIT, 12-14.5GHz Subsampling PLL with 150µW Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator,” IEEE International Solid-State Circuit Conference (ISSCC), Feb. 2020. (* Equally-Credited Authors)
● J. Kim*, H. Yoon*, Y. Lim*, Y. Lee, Y. Cho, T. Seong, and J. Choi, “A 76fsrms Jitter and −40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization,” IEEE International Solid-State Circuit Conference (ISSCC), Feb. 2019. (* Equally-Credited Authors)
● H. Yoon, J. Kim, S. Park, Y. Lim, Y. Lee, J. Bang, K. Lim, and J. Choi, “Fractional-N Frequency Synthesizer Supporting Multiple Frequency Bands for Backward-Compatible 5G Using a Frequency Doubler and Injection-Locked Frequency Multipliers,” IEEE International Solid-State Circuit Conference (ISSCC), Feb. 2018.
● J. Kim, Y. Lim, H. Yoon, Y. Lee, Y. Cho, T. Seong, and J. Choi, “An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally-Spaced Voltage Comparators,” IEEE Journal of Solid-State Circuits (JSSC), Dec. 2019, invited from IEEE 2019 International Solid-State Circuits Conference (ISSCC).
● H. Yoon, S. Park, and J. Choi, “A Low-Jitter Injection-Locked Multi-Frequency Generator Using Digitally-Controlled Oscillators and Time-Interleaved Calibration,” IEEE Journal of Solid-State Circuits (JSSC), Feb. 2019

[Awards/ Honors/ Memberships]

● TPC member of IEEE International Solid-State Circuits Conference (ISSCC), since 2023.
● IEEE SSCS Predoctoral Achievement Award Winner, 2019~2020.
● IEEE ISSCC Student-Research Preview (SRP) Award Winner, 2018.
● IEEE SSCS Student Travel Grant Award (STGA), 2017~2019.
● Samsung Human-Tech Paper Award (In total 3 awards, 2017, 2018, and 2019)
● Global Ph.D. Fellowship, National Research Foundation of Korea (NRF), Korea, 2015.
● Nine Bridge and Star Fellowship, UNIST, Korea, 2014.