교원소개

The Digital Processor & System-on-Chip (DiPS) Lab focuses on HW-friendly algorithm optimizations, digital computing architectures, and circuit implementations for intelligent computing systems. Our mission is to bridge the gap between algorithmic innovation and hardware realization by co-designing across algorithm, architecture, and circuit levels. By integrating research efforts, we aim to develop digital systems that enable next-generation applications.

 

[Curriculum Vitae]

● 2025 ~ Present: Assistant Professor, Department of Electrical Engineering, UNIST
● 2024 ~ 2025: Postdoctoral Researcher, POSTECH
● 2023 ~ 2023: Visiting Researcher, University of Michigan, USA

 

[Education]

● 2024: Ph.D. Electrical Engineering, POSTECH
● 2020: M.S. Electrical Engineering, POSTECH
● 2018: B.S. Electrical Engineering, POSTECH

 

[Research Keywords and Topics]

● Digital VLSI design
● Domain-specific computing systems
● HW/SW co-design
● Embedded System-on-Chip
● AI accelerator design
● Next-generation wireless communications

 

[Publications (selected)]

● D. Kam, M. Yun, S. Yoo, S. Hong, Z. Zhang, and Y. Lee, “Panacea: Novel DNN accelerator using accuracy-preserving asymmetric quantization and energy-saving bit-slice sparsity,” IEEE International Symposium on High-Performance Computer Architecture (HPCA), Las Vegas, NV, USA, Mar. 2025.

● D. Kam, S. Yun, J. Choe, Z. Zhang, N. Lee, and Y. Lee, “A 21.9 ns, 15.7 Gbps/mm^2 (128, 15) BOSS FEC decoder for 5G/6G URLLC applications,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, Feb. 2024.

● D. Kam, B. Y. Kong, and Y. Lee, “Low-latency SCL polar decoder architecture using overlapped pruning operations,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 3, pp. 1417-1427, Mar. 2023.

● D. Kam, B. Y. Kong, and Y. Lee, “A 1.1µs 1.56Gb/s/mm^2 cost-efficient large-list SCL polar decoder using fully-reusable LLR buffers in 28nm CMOS technology,” IEEE Symposium on VLSI Technology and Circuits (VLSI), Honolulu, HI, USA, June 2022.

● D. Kam*, J. G. Min*, J. Yoon, S. Kim, S. Kang, and Y. Lee, “Design and evaluation frameworks for advanced RISC-based ternary processor,” IEEE/ACM Design, Automation and Test in Europe (DATE), Antwerp, Belgium, Mar. 2022.

 

[Awards/ Honors/ Memberships]

● Best Paper Award, Samsung-POSTECH Research center, 2024
● Postdoctoral Fellowship (PIURI), granted by POSTECH, 2024
● POSTECHIAN Fellowship, granted by POSTECH EE, 2024
● International Research Scholarship, granted by KIAT (SNU), 2022
● IEEE SSCS Seoul Chapter Award (Best Design Award), ISOCC, 2020
● Samsung Humantech Encouragement Paper Award, 2019