세미나 및 강연

Abstract:
A network-on-chip (NoC), the de-facto communication backbone in manycore processors, consumes a significant portion of total chip power, competing against the computation cores for the limited power and thermal budget. On the other hand, overall system performance of manycore chips increasingly relies on on-chip latency and bandwidth as core counts scale. This talk will explore a design methodology of such NoCs, with the focus of the scalable platform design.
I will first introduce NoC router microarchitecture for those who are not familiar with NoCs. Then, in the second half of my talk, I will present my PhD research on a design methodology for scalable and reconfigurable NoCs.

Speaker Bio:
Mr. Sunghyun Park is a Research Scientist at Intel Labs in the definition of IoT-on-Chip. Before joining Intel, he studied network-on-chip (NoC) design methodology at MIT CSAIL. Mr. Park received the B.S degree in electrical engineering from KAIST in 2009, and the S.M. and Ph.D. degrees in electrical engineering and computer science from MIT in 2011 and 2014, respectively.