Research
2026년 05월 12일 화요일
Revolutionizing Semiconductor Design: AI Cuts Development Time from Months to Just One Day
Abstract Artificial Intelligence (AI) has been increasingly utilized across various fields, including communications, healthcare, and Computer-Aided Design (CAD). However, AI has shown relatively limited advances in analog and RF circuit design, which are critical for modern communication systems such as 5G due to their higher complexity and nonlinear characteristics. For example, the Inductor-Capacitor Voltage-Controlled Oscillator (LC-VCO) is a crucial component in frequency synthesizers, determining the performance of RF systems, including high data transmission rates and wide bandwidth. In fact, LC-VCO design is challenging due to the high parameter variability and complex interactions between design variables, making it challenging to optimize parameters to meet target specifications. Thus, this study proposes a comprehensive LC-VCO design methodology compatible across multiple process nodes and supports optimization down to the layout level. We use Reinforcement Learning (RL) to navigate the nonlinear design space efficiently for schematic optimization and apply an algorithm from Gradient Descent to optimize the design at the physical layout level. We highlight that the versatility of our methodology is demonstrated by producing optimized Figures of Merit (FoM) across various technology nodes and frequency ranges, showcasing its potential as a universal design tool accessible to all users. A team of researchers from UNIST and Kyungpook National University (KNU) has unveiled a pioneering AI system capable of completing the complex design of high-performance semiconductor circuits in just one day—an achievement that drastically reduces the traditional development timeline, which can take several months. Led by Professor Heein Yoon of UNIST’s Department of Electrical Engineering and Professor Taigon Song of KNU, the team developed an integrated AI platform that automates the entire process—from schematic design to physical chip layout. This breakthrough technology streamlines a typically multi-stage, resource-intensive task, offering faster, more efficient, and highly optimized circuit design solutions. The initial focus was on the design of the Inductor-Capacitor Voltage-Controlled Oscillator (LC-VCO), a critical component in 5G and emerging 6G communication systems. LC-VCOs generate the carrier signals essential for high-speed data transmission. Designing these circuits involves balancing numerous variables—such as inductor and transistor sizes—to minimize noise and power consumption. However, translating schematic designs into physical layouts often introduces parasitic effects that can impair performance. The new model integrates circuit schematic optimization with physical layout design, addressing these challenges holistically. During the schematic phase, reinforcement learning algorithms explore various parameter configurations to meet specific frequency and performance targets. Subsequently, in the layout phase, the system employs gradient descent methods to iteratively refine physical design parameters—such as wire widths and spacing—to enhance overall circuit performance. Gradient descent, a well-established optimization technique, incrementally adjusts design variables by following the gradient of the objective function toward an optimal solution. This integrated approach drastically accelerates the design process. Tasks that previously required up to 119 hours can now be completed in approximately 28.5 hours—reducing the overall time by over 76%. Moreover, the system’s adaptability across different semiconductor process nodes is enabled by transfer learning. Models trained on one technology node (e.g., 65nm) can be efficiently adapted to others (such as 40nm or 28nm), using just around 10% additional data. This AI-driven methodology not only shortens development cycles and reduces costs but also addresses the industry’s growing need for efficient design automation amid a global talent shortage. By ensuring high performance while minimizing manual effort, this technology is poised to significantly impact the production of next-generation communication and AI chips. The researchers anticipate expanding this framework beyond LC-VCOs to automate various analog and RF circuit designs, further accelerating innovation in semiconductor technology. The research was led by Sungjin Kim of UNIST and Hyunsoo Lee of KNU, who served as co-first authors, with additional contributions from Hong Seong-min of KNU. The findings of this research have been published online in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) on April 3, 2026. The study has been supported by the Ministry of Science and ICT (MSIT), the National Research Foundation of Korea (NRF), the Ministry of Education (BK21 Four), the Ministry of Trade, Industry and Energy (MOTIE), the Semiconductor Design Education Center (IDEC), Samsung Electronics, Axion Co., Ltd., and the Institute for Information & Communications Technology Planning & Evaluation (IITP). Journal Reference Sungjin Kim, Hyunsoo Lee, Seongmin Hong, et al., "A Framework of Automated LC-VCO Design with Physical Layout Based on Reinforcement Learning, IEEE TCAD, (2026).
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