Seminar

 
 
Abstract:
In the past few decades, there has been significant progress in the development of neural recording systems with fast advance in electronics and micro-mechanical-systems (MEMS) technologies. The number of simultaneous recorded neurons has been doubled at every 7.4 years, following a trend similar to Moore’s law. While various neural interface systems such as neural prosthetics can take the advantage of such rapid growth of the technologies, it is particularly beneficial to the comprehensive neuroscience research since high quality and parallel monitoring over a large number of neurons within small volume of brain can solely provide in-depth understanding brain’s structure and activities.
This talk focuses on developing system architectures and associated electronic circuits for a next generation neuroscience research tool, i.e. a massive-parallel neural recording   system capable of recording 1,024 channels simultaneously. Three interdependent research topics addressing major challenges in realization of the massive-parallel neural recording microsystems: minimization of energy and area consumption while preserving high quality in electrical recordings will be covered.
First, a modular 128-channel Δ-ΔΣ analog front-end (AFE) using the spectrum shaping technique will be introduced to propose an area-and energy efficient solution for neural recording AFEs. The fabricated AFE is expandable to a 1,024-channel parallel recording system via hybrid assembly with the customized 3-dimension platform consisting of multi-shank probes, interposers, and silicon-encapsulation. The AFE achieved 4.84 fJ/C−s·mm² figure of merit that is the smallest the area-energy product among the state-of-the-art multichannel neural recording systems.
Second, an on-chip mixed signal neural signal compressor will be proposed to reduce the energy consumption in handling and transmission of the recorded data since this occupies a large portion of the total energy consumption as the number of parallel recording increases. The compressor reduces the data rates of two distinct groups of neural signals that are essential for neuroscience research: local field potentials (LFP) and action potentials (AP) without loss of informative signals. As a result, the power consumptions for the data handling and transmissions of the LFP and AP were reduced to about 1/5.35 and 1/10.54 of the uncompressed cases, respectively. In the total data handling and transmission, the measured power consumption per channel is 11.98 µW that is about 1/9 of 107.5 µW without the compression.
Finally, a compact on-chip dc-to-dc converter with constant 1 MHz switching frequency will be suggested to provide reliable power supplies and enhance energy delivery efficiency to the massive-parallel neural recording systems. The dc-to-dc converter has only predictable tones at the output and it exhibits > 80% power conversion efficiency at ultra-light loads, < 100 µW that is relevant power most of the multi-channel neural recording systems consume.
 
Bio:
Sung-Yun Park received his B.S. in Electrical Engineering from Pusan National University, Busan, Korea in 2005, and his M.S. in Electrical Engineering from Korean Advanced Institute of Science and Technology, Daejeon, Korea in 2008, where he was involved in photonic device research. From 2008 to 2010, he worked for the Fairchild Semiconductor, Bucheon, Korea, as a high voltage mixed-signal integrated circuit designer. He continued his study in integrated circuits in Cornell University, Ithaca, NY and received the M. Eng. in Electrical and Computer Engineering in 2011, and his a Ph.D. in Electrical Engineering at the University of Michigan in 2016. He is currently a research fellow in the University of Michigan. His current research interests are in low power, low noise mixed-signal integrated circuits and power management circuits for biomedical systems.