Notice

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ICSL(Prof. Jaehyouk Choi)’s paper “A Low-Integrated-Phase-Noise 27–30-GHz Injection-Locked Frequency Multiplier with an Ultra-Low-Power Frequency-Tracking Loop for mm-Wave-Band 5G Transceivers” has been accepted for publication in IEEE Journal of Solid-State Circuits, which is the most prestigious journal in the field of semiconductor circuits. The authors are Seyeon Yoo, Seojin Choi, Juyeop Kim, Heein Yoon, Yongsun Lee, and Jaehyouk Choi.

This work presented a new LO-generator architecture for multi-standard cellular transceivers which is capable of supporting 5G communications as well as 2G – 4G standards. The developed LO generator achieved ultra-low IPN, which can satisfy the stringent requirement of the 5G standard. As a core circuit, a mm-band frequency synthesizer was designed and tested using TSMC’s 65nm CMOS technology.

 

Article title: A Low-Integrated-Phase-Noise 27–30-GHz Injection-Locked Frequency Multiplier with an Ultra-Low-Power Frequency-Tracking Loop for mm-Wave-Band 5G Transceivers

Authors: Seyeon Yoo, Seojin Choi, Juyeop Kim, Heein Yoon, Yongsun Lee, and Jaehyouk Choi

Journal title: IEEE Journal of Solid-State Circuits (JSSC)

IF: 4.181 (JCR 2016)