Notice

ICSL (Prof. Jaehyouk Choi)’s paper “A PVT-Robust Low Reference Spur Injection-Locked Clock Multiplier Using a Voltage-Domain Period-Calibrating Loop” has been accepted for presentation at the forth coming Symposium on VLSI Circuits 2016 which will be held in Hawaii.

Symposium on VLSI Circuits is one of the three major conferences on semiconductor circuits, along with ISSCC(International Solid-State Circuits Conference) and IEDM(International Electron Devices Meeting). In this work, the authors designed a new clock generator for smartphones, which had very low-level spurs as well as low jitter by overcoming conventional limitations of the architecture of an injection-locked clock multiplier. The prototype circuit was fabricated using a TSMC 40-nm CMOS process.

 

Authors: Yongsun Lee, Heein Yoon, Mina Kim and Jaehyouk Choi

Title: A PVT-Robust Low Reference Spur Injection-Locked Clock Multiplier Using a Voltage-Domain Period-Calibrating Loop

Conference: 2016 IEEE Symposium on VLSI Circuits

Presentation date: June, 2016